In the fabrication of microelectronic semiconductor devices on a wafer substrate, such as silicon, to form an integrated circuit (IC), various metal layers and insulation layers are deposited thereon in selective sequence. The insulation layers, e.g., of silicon dioxide, silicon oxynitride (SiO.sub.x N.sub.y), fluorinated silicate glass (FSG), also called fluorinated silicon oxide, spin-on glass (SOG), etc., serve as electrical insulation between metal layers, e.g., intermetal dielectric (IMD) layers, as protective layers, as gap filling layers to achieve planarization (layer flatness) in the wafer substrate, and the like, as the case may be. The individual layers are deposited by conventional technique such as plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure CVD, etc.
Typically, a first level metal layer, e.g., disposed on a silicon substrate containing devices, is separated by one or more insulation layers from a second level metal layer thereabove. This in turn may be separated by one or more further insulation layers from a third level metal layer thereabove, etc. These metal layers are interconnected by metallization through vias or small holes or apertures etched in the intervening insulation layers.
For this purpose, the stacked layers undergo photolithographic processing to provide a pattern thereon consonant with the IC design, e.g., to form vias. The top layer on the wafer substrate is covered with a photoresist layer of photo-reactive polymeric material for patterning via a mask. Light such as visible or ultraviolet (UV) light is directed through the mask onto the photoresist layer to expose it in the mask pattern. The polymeric material of the photoresist layer is transparent to the light yet photo-reactive to change its chemical properties, i.e., by photo-initiated reaction, thereby permitting its patterning.
An antireflective coating (ARC) layer such as an organic ARC layer, e.g., of light absorbing polymer, such as polyimide, is usually provided at the top portion of the wafer substrate to minimize reflection of light back to the photoresist layer for more uniform processing.
The photoresist may be of negative or positive type. In a negative photoresist, the exposed (polymerized) areas become insoluble while the unexposed (unpolymerized) areas dissolve in a later applied developer liquid. In a positive photoresist, the exposed (degraded) soluble areas dissolve in the developer liquid while the unexposed (insoluble) areas remain. In both instances, the photoresist material remaining on the wafer substrate forms the pattern to serve as a mask for etching in turn of the pertinent layers.
Where a layer material is of different physical and chemical characteristics from that of adjacent layers, its etching process is also different therefrom, e.g., in forming vias in dielectric layers to connect neighboring level metal layers. The etching is desirably anisotropic (high rate vertical direction etching and low rate or inhibited horizontal direction etching), as distinguished from isotropic (etching the exposed surfaces equally in all directions), for providing an etched structure of uniform vertical wall geometry or profile. Etching may be effected by wet etching (solution) or dry etching (plasma etching or reactive ion etching) technique, depending on the physical and chemical characteristics of the material being etched and of the neighboring material.
For maximizing the integration (connection) of device components in the available area on the wafer substrate to fit more components in the same area, increasing miniaturization is required. As narrower metal lines and closer pitch dimensions are needed to achieve increasingly dense packing of the components, they become more vulnerable to defects at the minute tolerances involved. This has become apparent as IC miniaturization has increased to what is now called very large scale integration (VLSI) at sub-quarter micron (0.25 micron, i.e., 250 nanometer (nm) or 2,500 angstrom) dimensions.
By comparison, visible light has a wavelength spectrum of 400-700 nm (4,000-7,000 angstroms), and UV light has a wavelength spectrum of 100-400 nm (1,000-4,000 angstroms). Generally, mid UV (MUV) light has a wavelength of about 365 nm, while deep UV (DUV) light has a wavelength of about 248 nm or less.
At sub-quarter micron sizes, the desired high aspect ratios (depth to width) associated with photolithographic processing to form apertures or windows, fine conductive lines, etc., in various layers of the wafer substrate, require very strict tolerances to prevent undesired defects such as touching of closely spaced apart components that can cause short circuiting, etc.
During travel of the mask patterned incident light from the radiation source through the photo-reactive polymeric material of the photoresist layer, it is progressively absorbed as it photo-initiates reaction in the exposed pattern areas. As some incident light reaching the ARC layer is not absorbed thereby, but rather is reflected and scattered back into the photoresist layer, there is interference with the incident light and formation of standing waves.
Contaminants that are incompatible with the photo-reactive polymeric material can migrate into the photoresist layer from the ARC layer or other vicinal layer. These contaminants can poison the photoresist layer, e.g., undergo interfering reactions therewith, causing non-uniformity of the reaction therein by extraneous chemical interaction with the polymeric material. This is commonly called photoresist poisoning and leads to the formation of a photoresist footing where a positive photoresist is used, or to a photoresist pinching where a negative photoresist is used.
Specifically, upon development, the exposed pattern areas of the photoresist layer have a photoresist profile or structure with non-uniform (non-vertical) side walls. After etching, the photoresist footing or photoresist pinching problem leads to imperfect transfer of the photoresist pattern to the underlying layer or layers, and ultimately limits the minimum spatial resolution since the etched structure is imprecise compared to the desired IC design.
Some examples of the fabrication of semiconductor devices are shown in the following prior art.
[1] U.S. Pat. No. 3,884,698 (Kakihama et al.), issued May 20, 1975, discloses a semiconductor substrate having in turn an insulation layer, an opaque metal ARC layer, and a photoresist layer. The metal ARC layer absorbs most of the incident light so that only a small part reflects back to the photoresist layer. The problem involved is that interference between incident and reflected light in the photoresist produces standing waves with minimum exposure nodes and maximum exposure antinodes. Light of an intensity for correct antinode exposure causes node underexposure, so that upon development the photoresist pattern is not completely open for accurate etching of underlying layers. Conversely, light of increased intensity for node exposure and complete opening of the pattern, causes antinode overexposure and poor pattern definition. This is alleviated by choosing the insulation and metal ARC layer thicknesses so as to cancel the reflected light, suppress the interference and reduce the standing wave amplitude.
[2] U.S. Pat. No. 4,491,628 (Ito et al.), issued Jan. 1, 1985, discloses a positive or negative photoresist, depending on the developer, for deep UV photolithography to attain nearly vertical walls. It is formed from a polymer with acid groups that undergo acidolysis causing changes in polarity (solubility) of the exposed and unexposed regions, a photo-initiator that generates acid upon radiolysis, and a sensitizer, e.g., a dye, that absorbs radiation to alter the sensitivity of the photo-initiator.
[3] U.S. Pat. No. 4,587,138 (Yau et al.), issued May 6, 1986, discloses a semiconductor substrate having in turn an insulation layer, an aluminum layer, a dye-containing SOG layer wherein the dye causes the SOG layer to function as an ARC layer, and a photoresist layer. The dye-containing SOG ARC layer permits antireflective photolithographic patterning as well as alloying and hermetic passivation at temperatures above 200.degree. C. while inhibiting formation of surface hillocks and internal voids in the aluminum layer. In the passivation step, a silicon oxynitride hermetically sealing layer is added. The dye-containing SOG ARC has the advantage over an organic, e.g., polyimide, ARC, that if the photoresist process must be reworked, only the photoresist is stripped and not the SOG ARC.
[4] U.S. Pat. No. 4,820,611 (Arnold, III et al.), issued Apr. 11, 1989, discloses the reducing of reflected light from a metal layer on an IC structure back to a photoresist layer during photolithographic patterning, by placing a TiN (titanium nitride) ARC layer between the metal and photoresist layers. The TiN ARC layer thickness depends on the radiation wavelength and metal layer optical properties to reduce standing wave interference due to light reflection and scattering. TiN ARC use is distinguished from metal or refractory ARC use and from organic, e.g., dye-containing polyimide, ARC use.
[5] U.S. Pat. No. 4,981,530 (Clodgo et al.), issued Jan. 1, 1991, discloses the use of SOG for an organic insulation layer on a semiconductor substrate. Water is reacted with an amino alkoxy silane in a solvent, and the resulting solution is aged, spin coated on the substrate and cured in an oxygen-free, inert nitrogen atmosphere to a ladder type silsesquioxane polymer. This SOG material is distinguished from known organic insulation layer materials such as polyimide resins which exhibit poor planarizing characteristics and polysiloxanes which show stress-induced cracking and poor adhesion.
[6] U.S. Pat. No. 5,219,788 (Abernathey et al.), issued Jun. 15, 1993, refers to the five above discussed U.S. Pat. No. [1] 3,884,698 (Kakihama et al.), U.S. Pat. No. [2] 4,491,628 (Ito et al.), U.S. Pat. No. [3] 4,587,138 (Yau et al.), U.S. Pat. No. [4] 4,820,611 (Arnold, III et al.), and U.S. Pat. No. [5] 4,981,530 (Clodgo et al). It discloses a semiconductor substrate having in turn a metal bilayer of Ti and Al/Cu/Si, a TiN ARC layer, a silicon-containing barrier layer of Si, SiO.sub.2 or SOG, and a deep UV photoresist layer for high density photolithographic patterning with reduced line width and pitch of device components, while avoiding photoresist webbing (photoresist footing) formation.
In [6] U.S. Pat. No. 5,219,788 (Abernathey et al.), the photoresist is of the type that generates acid groups on exposure per said [2] U.S. Pat. No. 4,491,628 (Ito et al.). When the barrier layer is formed of SOG, it can be applied to the TiN ARC layer per said [5] U.S. Pat. No. 4,981,530 (Clodgo et al.). The barrier layer prevents interaction between the TiN of the ARC layer and acid groups of the photoresist layer. The TiN ARC layer provides adhesion for the barrier layer and prevents silicon transport from the barrier layer to the metal bilayer during high pressure processing. During patterning, of course, the TiN ARC layer suppresses light reflection back to the photoresist.
DARC (dielectric antireflective coating) layers, particularly those based on silicon oxynitride, have multiple advantages at several mask levels in the semiconductor fabrication. They can be used in destructive interference and absorption modes and their composition and properties can be well controlled during the deposition process. In some applications, they can also be employed as hard masks in the etch process following a given photolithographic step. It is expected that they will at least partially replace organic spin-on ARC materials in the near future.
A disadvantage of silicon oxynitride films (layers) lies in their incompatibility with modern DUV (deep UV) photoresist systems due to reactive contaminants that are present therein, i.e., reactive nitrogenous substances (including reactive nitrogen itself and attendant self-generating reactive functional group-containing contaminant compounds thereof with other contaminating precursor constituents). These reactive nitrogenous substances tend to migrate or diffuse out of the silicon oxynitride layer and chemically interact with constituents of the polymeric material of the photoresist layer.
As earlier noted, such chemical interaction, commonly called photoresist poisoning, leads to photoresist footing or photoresist pinching, i.e., non-uniform side walls of the photoresist profile on the underlying substrate after the photolithographic exposure and development process has been performed. The photoresist footing or photoresist pinching problem leads to imperfect transfer of the photoresist pattern to the underlying substrate and ultimately limits the minimum spatial resolution of IC components.
Therefore, a conventional silicon dioxide cap layer is usually deposited on the silicon oxynitride layer as a spacer layer to minimize reactive nitrogenous substance out-diffusion. However, this silicon dioxide cap layer is typically also deposited with a reactive nitrogen-containing species, such as by PECVD technique using silane (SiH.sub.4) with oxygen and nitrogen or nitrous oxide (N.sub.2 O), and/or remaining nitrogen may diffuse from the silicon oxynitride layer into the silicon dioxide cap layer. Both effects can again cause the above described poisoning phenomena.
While the matter is not fully understood at this time, it is believed that reactive contaminants such as hydrogen and nitrogen remain as precursor constituents in silicon dioxide based layers consequent their deposition, e.g., by PECVD technique, using silane (SiH.sub.4) with nitrous oxide, and the like. In the presence of such reactive nitrogen, it is considered that self-generating reactive contaminant compounds thereof, such as amines, are formed with attendant hydrogen and/or other species that remain as contaminating precursor constituents. It is believed that such reactive nitrogen and such self-generating reactive contaminant compounds out-diffuse to collect at the interface with the overlying photoresist layer to cause such poisoning problems.
As used in the specification and claims, the term "reactive nitrogenous substance" contemplates reactive nitrogen-containing substances including both reactive nitrogen itself and attendant self-generating reactive contaminant compounds thereof with other contaminating precursor constituents such as hydrogen (i.e., reactive nitrogen-containing contaminant compounds).
A typical prior art fabrication technique for forming a patterned conductive multilayer arrangement on a semiconductor substrate, which involves a dual damascene metallization scheme using a conventional organic ARC, includes the following steps:
(1) depositing an intermetal dielectric (IMD) insulation layer, e.g., of silicon dioxide, on an underlying semiconductor wafer substrate having a first level conductive layer, e.g., of metal, thereon, and then depositing a first organic ARC layer on the insulation layer and a first photoresist layer on the organic ARC layer, followed by patterning (photolithographic exposure and development) to open a contact hole (aperture) in the photoresist layer;
(2) subjecting the organic ARC layer to an open etch to deepen the aperture and expose the underlying insulation layer, whereby the aperture pattern in the photoresist layer is widened due to the non-selectivity of the open etch process;
(3) subjecting the insulation layer to dielectric etching, using the photoresist layer as a mask, to deepen the widened aperture and form a via exposing the underlying first level conductive layer, and then stripping the photoresist layer and organic ARC layer;
(4) depositing a second organic ARC layer on the insulation layer, whereby the via becomes filled with residual organic ARC material, and then depositing a second photoresist layer on the organic ARC layer, followed by patterning (photolithographic exposure and development) to open an interconnect trench in the photoresist layer surrounding the via;
(5) subjecting the organic ARC layer to an open etch to deepen the trench and expose the underlying insulation layer, while also removing the upper portion of the residual organic ARC material that fills the via in the insulation layer, whereby the trench pattern in the photoresist layer is widened due to the non-selectivity of the open etch process;
(6) subjecting the insulation layer to dielectric etching to deepen the trench further and form a corresponding trench in the insulation layer, which leaves fences surrounding the via because of the interfering presence of residual organic ARC material in the via, and then stripping the photoresist layer and organic ARC layer;
(7) wet cleaning the insulation layer, and depositing a second level conductive layer, e.g., of metal, on the insulation layer to overfill the via and trench pattern created therein and form a conductive contact with the first level conductive layer exposed at the via; and
(8) subjecting the second level conductive layer to chemical mechanical polishing (CMP) to remove surplus conductive material and expose the surface of the insulation layer typically with some overpolishing.
It is clear from the foregoing that the organic ARC open etching leads to width control problems and that the fences left in the insulation layer may lead to the formation of voids in the conductive layer and consequent reliability problems.
It is desirable to have an arrangement of silicon oxynitride as a DARC layer for a photoresist layer during fabrication of a semiconductor device which prevents out-diffusion of reactive nitrogenous substances so as to avoid poisoning the photoresist layer and consequent photoresist footing or photoresist pinching problems causing imperfect pattern transfer into the underlying substrate that limits the minimum spatial resolution of components on the device, especially if this is attained while reducing the manufacturing costs.